The fabrication of integrated circuits involves subjecting a semiconductor substrate to numerous processes, such as photoresist coating, photolithographic exposure, photoresist development, etching, polishing, and heating or “thermal processing.” In certain applications, thermal processing is performed to activate dopants in doped regions (e.g., source and drain regions) of the substrate. Thermal processing includes various heating (and cooling) techniques, such as rapid thermal annealing and laser thermal processing. Where a laser is used to perform thermal processing, the technique is sometimes called “laser thermal processing” or “laser annealing.”
Laser thermal processing involves irradiating a substrate with a localized beam of intense radiation to bring the substrate surface from a relatively low temperature (e.g., 400° C.) to a relatively high temperature (e.g., 1,200° C.) quickly. The high temperature regime has a short duration so that the heat can dissipate into the substrate bulk quickly.
Laser thermal processing may be used to activate dopants in source/drain regions of transistors formed in a silicon wafer. The source/drain regions are typically formed by exposing areas of a silicon wafer to an electro-statically accelerated ion beam containing ions such as boron, phosphorous or arsenic ions, depending upon whether an N-type field effect transistor (NFET) or P-type field effect transistor (PFET) is to be formed. After implantation, the dopant atoms are largely interstitial, do not form part of the silicon crystal lattice, and are electrically inactive. Activation of these dopant atoms may be achieved by raising the substrate temperature high enough and for a period of time long enough for the crystal lattice to incorporate the impurity atoms. The optimum length of time depends on the maximum temperature. However, during the activation thermal cycle, the impurities tend to diffuse throughout the lattice causing the distribution to change from one approximating an ideal step profile achieved during implant to a profile having a shallow exponential fall-off after a long annealing cycle.
By employing higher annealing temperatures and shorter annealing times as are characteristic of laser thermal processing, it is possible to reduce dopant diffusion and retain the abrupt step-shaped dopant distribution achieved after the implant step. The continuous reduction in transistor feature sizes has lead to a process called laser spike annealing, which employs a CO2 laser beam formed into a long, thin image that is raster scanned across the wafer. In a typical configuration, a 0.1 mm wide beam is scanned at 100 mm/s over the wafer surface to produce about a 1 millisecond dwell time for the annealing cycle. A typical maximum temperature during this annealing cycle might be about 1350° C. In the 1 millisecond duration necessary to bring the wafer surface up to the annealing temperature, only about 100-200 micrometers of material nearest the upper surface is heated. Consequently, the bulk of the 800 micrometer thick wafer serves to cool the irradiated surface almost as quickly as it was heated after the laser beam is focused elsewhere.
At the outer edge of the wafer, less wafer material is available to conduct heat away from the irradiated surface. As a result, uncontrolled stresses may be introduced near the substrate's outer edge. Uncontrolled stresses may result in catastrophic mechanical failure leading to substrate breakage.
Accordingly, it is desirable to provide semiconductor substrates that better withstands irradiation induced stress as compared to semiconductor substrates produced through conventional laser spike annealing techniques. In addition, it is desirable to provide methods for fabricating integrated circuits that minimize semiconductor substrate breakage or damage resulting from annealing stress. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.